Multi-core processors include multiple independent central processing units (“CPUs”), sometimes referred to as “cores.” The cores in a multi-core processor may have access to a dynamic random-access memory (“DRAM”) device. A DRAM device may have a DRAM array comprised of memory cells organized into a series of rows. The rows of memory cells may be further organized into one or more columns. In some DRAM devices, if two or more cores attempt to access the same row of the same DRAM array at the same time, a row conflict may be generated. The row conflict may cause an error as it might be from a different column. To reduce the probability of a row conflict, one processor core may be instructed to wait until a DRAM device access performed by another core has been completed. Overall processing speeds of the multi-core processor may be reduced, including increased overall latency, when one core is instructed to wait until another core completes a memory access.
Unless otherwise indicated herein, the materials described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.